Video IP Codec Modelling Engineer

The Role:

We, HW video IP team located in Markham, Ontario, Canada, are looking for a SMTS level design engineer to perform video Codec modelling and algorithm development! As a member of the codec modelling team, you will be responsible for crafting the future of 9our design solutions with advanced algorithm modelling and quality optimization to drive a willing solution now and future IP generations.

The Person:

An organized, hardworking self-starter, strong interest interested in video codec architecture, algorithm, quality assessment and functional verification.

Good interpersonal skills (verbal and written.

Key Responsibilities:

• Core codec modelling team member.
• Encode algorithm, architecture, quality analysis and optimization.
• Decode architecture modelling.
• Work spanning among all current AVC, HEVC, VP9, AV1 codec and upcoming newer standards.
• Provide support and triage algorithm and functional issues to IP and post-silicon teams.
• Think creatively!

Preferred Experience:

• 10+ years of hands on experience and expertise in video codec development.
• 5+ years of hands on architecture, modelling, and FW along with verification experience.
• Excellent working experiences and knowledge among various video codecs: H.264, H.265, VP9, AV1, and other emerging standards.
• Expertise in C, C++ along with design verification skillset in an ASIC design environment.
• Proven and strong analytical and problem solving skills.
• Excellent technical leadership to lead others and drive development.
• Hands on experience in script and automation development.

Academic Credentials:

Master in EE or Computer Engineering, or equivalent degree or above