SoC Front End Integration Engineer- 118822

 

Developing great technologies requires passion and true appreciation for design and innovation. If you share our passion, you have an opportunity to join our SoC FIENT team of Radeon Technologies Group.

 

Key Responsibilities:
- RTL Design in Verilog: analyze RTL Verilog files for the DFP and maintain the regression flow.
- Synthesis with timing driven placement and design for power (DFP)
- Static Timing Analysis and Optimization
- Formal verification of synthesized netlists
- Implement the Design for Power flow to describe the power intent (UPF) for IP’s and on the SoC Chip level
- Maintain and create various scripts to support the Design and Verification flows, this includes Unix, Perl, and TCL
- Scripting and Automation

 

Skills and Experience Requirements:
- Education in Electrical and/or Computer Engineering
- Basic understanding of Verilog coding
- Strong knowledge of scripting Linux/Unix environment, Perl, and TCL are preferred.
- Basic knowledge of the Physical Design (PD) process
- Strong organization, multitasking, problem-solving, and analytical skills are a must
- Must be a self-starter and able to independently drive tasks to completion
- Strong verbal and written communication skills
- Energetic, committed, and positive person who\'s willing to learn and develop in computing hardware electrical engineering