TITLE : SerDes Modelling Engineer

THE ROLE : The candidate will be a member of the high speed SerDes design team supporting the system simulation and implementation of future SerDes IPs in the 32Gbps+ range, especially in the PAM4 area. The focus of the activity will be centered around the modeling of the critical high-speed analog and digital blocks, definition of algorithms for calibration, adaptation, equalization, and development of abstracted models for link performance simulations.

THE PERSON : The ideal candidate will have :

• Analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation
• Strong/effective communication skills
• Hard working team-first mentality

RESPONSIBILITIES :

• Contribute to the modeling of various state-of-the-art, high-speed (32-64Gbps) analog/mixed-signal blocks for SerDes PHYs, specifically in the PAM4 area
• Develop models for link-level performance (BER, eye-opening) simulation of the PHY and application of the same to the development and optimization of performance.
• Documentation of algorithms and guidance of Analog, Digital, Firmware and Verification teams on the implementation/verification of the same
• Work closely in various domains, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure efficient implementation of the overall PHY architecture and algorithms and full coverage of the features
• Participate to the definition of development flows that improve efficiency and quality of execution

PREFERRED SKILL SETS & EXPERIENCE :

• A confirmed successful track record in micro-architecture, design, or modeling for SERDES
• Proven and hands-on knowledge of algorithms and adaptation/calibration/ clock and data recovery techniques for high-speed SERDES, especially in the area of PAM4
• Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink/Python) as well as Verilog-based.
• Good knowledge in high-speed SerDes design (signaling/equalization techniques, analog/mixed-signal circuit design, and signal integrity).
• Ability to dig into circuits and RTL or FW code to understand the detailed implementation

 

EDUCATION :

• BS or MSc Electrical or Computer Engineering; BSc Computer Science

 

AMD is a government contractor and subcontractor. As required by Executive Order, our US employees are required to be fully vaccinated against COVID-19 regardless of the employee’s work location or work arrangement (e.g., telework, remote work, etc.), subject to such exceptions as required by law. If selected, you will be required to be vaccinated against COVID-19 and submit documentation of proof of vaccination by December 8, 2021. AMD will provide additional information regarding what information or documentation will be needed and how you can request an exception from this requirement if you have a need for a religious and/or medical accommodation.