Title: ASIC Design Engineer

The Role : ASIC Design Engineer who will be involved in all aspects of IP RTL design.  

The Person : 

• Exhibits relentless commitment to help the team meet quality and development goals on schedule
• Drives to learn and perform at his or her highest potential in a technical capacity
• Thrives in both a team environment and in individual contribution
• Communicates openly and clearly in meetings, presentations, emails, and reports
• Able to learn independently and acquire new skills required for the job
• Flexible in working hours to accommodate working with co-workers in different time-zones
• Creative and innovator and thinker who loves technical problems and detail-oriented tasks

Responsibilities :

• IP RTL design for AMDs PCI Express (PCIe) IP used for all next generation server, clients, GPU and Semi-custom products.
• Work closely with IP and system architects to micro-architect cutting edge features.
• Apply low power design techniques to existing logic and maintain overall system performance. 
• Focus on timing, LINT and CDC closure to ensure high quality RTL. 
• Support verification and debug of the ASIC through out various stages of the project. 
• Jump into the lab and solve post silicon bring-up or customer issues.

Preferred Skilled Sets :

• Digital Design in RTL, Verilog HDL
• Verilog/VHDL/System Verilog
• Good understanding PCI Express and Computer Architecture is preferred. 
• Other technical knowledge such as C/C++, System Verilog, and UVM would be beneficial for testbench/simulation debug. 
• During bring up, some lab work with logic analyzer and oscilloscope might be required.
• Understanding of Linting / CDC tools, equivalence checks

Education Requirements

• Bachelor/Master in Electrical/Computer Engineering/Engineering Science or Computer Science.