Physical Design Engineer 92325

 

AMD has an exciting opportunity for a Silicon Design Engineer to join our (Physical Implementation & Integration) Design team making multibillion gates SOC’s in the latest bleeding edge foundry technology (5nm and below).

 

The Role:

We are looking for an Engineer with hands-on experience in chip level floorplanning, feedthrough topology planning, repeater insertion, top level port/pins assignment/alignment and source synchronous bus planning.

 

The Person: 

Our next new team member will be someone with excellent communication skills, strong interpersonal skills, and outstanding English writing, speaking and reading skills. If you are curious, hardworking and a good team player, please read on for more details about this opportunity!

 

Key Responsibilities:

This Engineer will have solid understanding of the following synthesis and physical design functions including:

• Timing/SDC constraints generation and management. Strong background in Constraint analysis and debug, using industry standard tools
• Low power design and implementation knowledge on power aware synthesis & pnr. Knowledge on voltage domain check will be a plus.
• Work with Physical Design team on Floor Plan, ram placement, timing closure and resolve congestion etc.
• Some exposure to DFT is a strong plus

 

Preferred Experience:

• Hands on experienced in EDA tools like DC and ICC2
• Hands on experienced in STA tools and technique for timing closure
• Understanding of floorplan and layout techniques for foundry rule compliant
• Experience in scripting with TCL, Perl or Python

 

Academic Credentials:

Bachelor’s Degree Electrical Engineering or related degree, Masters Degree preferred along with industrial experience in ASIC design and tapeout project experience.