Title : IOMMU Validation Engineer

The Role: 

We are hiring an enthusiastic individual for the validation of AMD’s IOMMU IP.  The successful candidate will drive post-silicon efforts for current and future of IOMMU implementations and be a key contributor to the exciting realm of virtualization development within AMD. 

As a key contributor to the success of AMD's IPs and SOCs, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry leading technologies to market. The NBIO IP Systems Engineering team is a key driving force in the successful development and rollout of AMD’s brand-new leading edge I/O and traffic enhancement technologies.  We are a growing team targeted at providing high quality architectural rollout to all of AMD’s products and achieve post-silicon success through teamwork and innovation.  Our team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

The Person:

The successful candidate will have excellent written and oral communication skills along with the ability to lead projects and drive tasks to completion with minimal supervision.  The candidate must be a team player with excellent interpersonal skills.  Leadership and mentoring skills a definite asset.

Key Responsibilities:

As an IP Validation Design Engineer, you will drive planning, verification, and debug of forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs.  This includes:

• Defining, documenting, executing, and reporting of IP functional test plans and validation strategies for multiple AMD products. 
• Investigating RTL, systems, firmware, and software level issues; driving for root cause and provide best system and product level solutions at all phases of product development from pre-silicon to production.
• Driving innovation of IP validation improvements, including tool and script development, technical and procedural methodology enhancement, and various internal and multi-functional technical initiatives.
• Engaging on pre-silicon verification efforts with multi-functional teams, including but not limited to Design Verification (DV), Diagnostics, FPGA-based Emulation, and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features.
• Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives.
• Low-level testing of PCIe hardware features using diagnostics, software tools, protocol/logic analyzers, oscilloscopes, and other test equipment.
• Developing knowledge of system architecture/debug and other internal IP’s.
• Supporting issues on customer platforms as requested by customer support teams.

Preferred Skill Sets:

• Experience in digital logic design/validation; verification or post-silicon verification.
• Experience with ASIC debug techniques and methodologies.
• Board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization.
• Strong programming/scripting skills (eg. C/C++, Ruby, Python).
• Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
• In-depth knowledge of PC architectures/PCIe protocol an asset.
• In-depth knowledge of PCIe Specification including ATS/PRI and asset.
• Experience with I/O translation and virtualization an asset.
• In-depth Knowledge of Caches/TLBs/Paging an asset.

Education:

Bachelors or master’s degree in Electrical or Computer Engineering