Key Qualifications

• We value proven ability in all aspects of ASIC implementation including Synthesis, DFT insertion, Floorplanning, Clock & Power distribution, Place and Route and all aspects of timing, electrical and physical signoff.
• Work with FE teams to understand the design architecture to drive optimal floorplanning and physical implementation through early RTL feedback.
• Use design knowledge and state-of-the-art physical construction & optimization flow to push performance, power, and Area (PPA) of GPU designs.
• Experience with multi-voltage, power gated and power retention will be an advantage.
• Your practical knowledge with hierarchical design approach, top-down design, budgeting, timing and physical convergence will be an asset.
• Showcase your experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
• Your depth of expertise with large GPU designs (>20M gates) with frequencies in excess of 1GHz utilizing state-of-the-art technologies will serve you well.
• We would like you to join our team if you have a detailed understanding of database management issues.
• From a CAD tool perspective, experience crafting Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.
• Familiar with various process-related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal management.

Description

Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle. Drive best in class PD construction and optimization recipes for performance, power and Area (PPA). Collaborate to drive methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and track progress. Be focal point for place and route drive the work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. Manage and resolve design and flow issues related to physical design, identify potential solutions and drive execution. Are you a confident problem solver who thrives under pressure to find new, creative solutions? Are you ready to help chart the future of Apple's ecosystem? If so, we are excited to hear from you.

Education & Experience

BSc/MSEE/M Eng/BEng or equivalent is required