Title: Front integration & Physical Design Manager

The Role:

In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. The DXIO FEINT/Implementation team is responsible for Synthesis, place & Route, Timing closure/CDC/LINT/DFx for very high speed (>2G) design with complex I/O clocking.

 

The Person:

As a Front integration & Physical Design Manager, you will lead a mid-size team of front-end integration and physical design engineers. You will work with a complementary team – architects, RTL design engineers, SoC design teams & managers from NBIO IP team. You will drive physical implementation of IP through the entire physical design flow, starting from Synthesis, constraint development, to achieve best PPA, while shortening the overall development schedule. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!

 

Key Responsibilities:

We are currently looking for a Front integration & Physical Design manager who will drive all implementation aspects of next generation IPs. This team deals with multiple I/O protocols including PCIe, SATA, Ethernet & Infinity Fabric link-layer.

This team is a group of highly experienced ASIC design engineers working on High speed (>2G) designs with very complex clocking infrastructures. The team owns implementation activities including Synthesis & DFT, floorplan, placement, clock tree synthesis, routing, STA closure.

The team will work on cutting edge IP for these I/O protocols to achieve physical implementation with best PPA, including developing reference floorplans, implementation scripts for SoCs worldwide, and support SoCs worldwide.

 

Technical Expertise:

CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python

 

Preferred Experience:

Leading a mid-size team, managing various technical aspects related to Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >=2GHz designs. Leading personnel, setting team goals, tasks, schedules, & best practices to improve efficiency, quality.

 

Academic Credentials:

Minimum, B.S with at least a decade of experience

or

M.S. in Electrical or Computer Engineering (or equivalent) with at least a dozen years’ experience preferred

 

Location:

Markham, Canada / Austin, TX / Santa Clara, CA

 

AMD is an inclusive employer dedicated to building a diverse workforce. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective provincial human rights codes throughout all stages of the recruitment and selection process. Any applicant who requires accommodation should contact AskHR@amd.com.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services.