TITLE : DFX Engineer (Design for Excellence) 

 

THE ROLE:

AMD is searching for an experienced DFX Engineer to join the fast-growing NBIO design team, and be responsible for defining, specifying, and implementing current and future DFX solutions for high-speed I/O IPs. The candidate will be involved in digital design and collaborate in the whole spectrum of areas include DFX, Firmware, Design verification, and Physical Design. The specific role will be to work on the micro-architecture and DFX strategy of lead IPs.

 

Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! Looking forward to welcoming you in the team!

 

THE PERSON:

• Possess in depth knowledge of entire design process from Design specification, DFx, front-end and back-end implementation
• Expertise on DFX area from test feautes, debug features to functional coverage/testing
• Knowledge of chip bus interfaces such as AHB, AXI and various standard peripherals & interfaces is a plus
• Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)
• Solid knowledge of industry standard tools and practices for Digital and Physical Design
• Quality-oriented mindset
• Strong and effective communication skills and team spirit
• Understanding in high-speed I/O protocols (PCIe, USB, SATA, Ethernet…)

 

 

KEY RESPONSIBILITIES:

• Micro-architecture of digital blocks and hardware/firmware partitioning
• Architect DFX strategy for chiplets and fuctional coverage
• Optimize RTL implementation from implementation perspective in cooperation with RTL and Architecture teams
• Optimization of physical implementation in cooperation with Physical Design team

 

PREFERRED EXPERIENCE:

• Experience with state-of-the-art industry standard digital tools
• Preferred experience in design with multiple clock domains
• RTL design experience with multi-clock, high frequency designs
• Knowledge in digital RTL Digital Design, Verificatoin and Implementation
• Definition Experience in DFT techniques like BSCAN, I/O interconnect testing, Scan, ATPG and PRBS testing
• Experience in high speed digital design 
• Experience in digital front-end implementation, including micro-arch.
• Experience with ATE bringup
• Experience with debug features like debug bus and on-chip logic analyzers
• Ample expertise on functional testing and coverage/DPPM analysis

 

EDUCATION:

• Master’s/Bachelors in electrical engineering or equivalent preferred