DESIGN VERIFICATION ENGINEER – GRAPHICS CORE IP

THE ROLE:

As a Member of Technical Staff Design Verification Engineer, you will work with leading industry tools and design & verification concepts to achieve full functional, performance & power verification closure on a variety of digital design blocks which are a part of the Graphics Core IP (GFXIP). You will work closely with architects, designers and other design verification engineers to author testplan for pre-silicon verification, planning & development of testbenches to exercise the design, write detailed testplans to cover new blocks and features, drive the development of test-cases and coverpoints or assertions to achieve verification closure. You will also own regression and coverage tracking & closure for the block(s) that you are responsible for.

A project usually has a year timeline and there are many products that the GFXIP is deployed into, including main-stream, mobile, workstation, machine-intelligence GPUs, APUs and gaming consoles.

THE PERSON:

Besides a passion for modern, complex processor architecture, digital design, and verification in general, these personal qualities are essential to success in this role:

• Excellent analytical and organizational skills
• Outstanding verbal & written communication
• A self-starter who excels at driving tasks to completion and enabling collaboration amongst team members
• Enjoys working in a dynamic, fast-paced environment located in Markham while interacting with multiple sites in North America & worldwide

KEY RESPONSIBILITIES:

• Work closely with the architect, RTL designers and other verification engineers to achieve verification closure within project schedules
• Be responsible for functional, power and performance verification of a block, including verification planning, execution and DV closure
• Develop and execute test and coverage plans to ensure the functional, performance and power completeness
• Create, reuse and debug testbenches, verification components and tests for verification of the design
• Drive verification methodology improvement initiatives and encourage adoption of better processes across the broader team
• Mentor and train junior design verification engineers and interns

PREFERRED EXPERIENCE:

• Minimum 5+ years of verification experience on large ASIC development projects
• Solid understanding of Computer Architecture and Digital Design concepts
• Very strong background in Verilog, System Verilog, C/C++/OOO coding techniques
• Experience working with UVM, OVM or equivalent
• Experience with constrained random verification, functional coverage and assertions
• Experience with formal verification is an added advantage
• Familiarity with scripting languages: perl/tcl/ruby/Bash/python
• Experience working with industry standards tools such Synopsys VCS, VC Formal, DVE, Verdi, GDB or equivalent
• Strong analytical skills and attention to detail

 ACADEMIC CREDENTIALS:

• Bachelor’s (or preferably Master’s) degree in Computer Engineering, Computer Science, Electrical Engineering or similar