TITLE : Design Verification Engineer

THE ROLE : This is an exciting opportunity to work on Design Verification in multiple industrial (PCIe/Virtualization) and AMD proprietary IP blocks environment

RESPONSIBILITIES:

• Execute a project independently with global teams to achieve pre-defined goals in time
• Understand logical design architecture and provide the analyzed data to architects for review
• Improve existing UVM test bench with advanced design verification methodology
• Bring up new design features
• Responsible for SOC design and design verification support.
• Accountable for project delivery.
• Establishes and maintains AMD's technological leadership position in an area
• Considered technical leader across project and departmental boundaries and has a proven track record for sustained innovation.
• Is responsible for projects or processes of significant strategic or commercial importance and for project/program results
• Deals with problems requiring cutting edge approaches and champions innovation across the organization
• Makes technical decisions that have a significant impact on product families, go to market strategies and customer satisfaction
• Provides consultative direction with management
• Coaches and mentors experienced staff
• Represents AMD to the outside technical community, partners and vendors
• Improve existing test bench to achieve the goals of reusability, configurability, and scalability
• Elevating current ASIC design verification quality and the simulation efficiency to higher level

REQUIREMENTS:

• Rich experience in constructing highly scalability, configurability and reusability DV test bench.
• Strong experience in ASIC design/verification related field in IP, Subsystem or SOC level
• Expertise in writing System Verilog and/or System C models for simulation
• Proven experience in writing UVM models, checkers and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus
• Experience composing test plan and validation vectors to ensure functional completeness
• Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
• Versatile in any one of the high level verification flow such as SV,  UVM, C++, etc. as well as knowledge of industry standard tools for verification
• Excellent communication skills (both written and oral)
• Strong problem solving skills

EDUCATION:

• Major in EE, CS or related, Master Degree 

AMD is a government contractor and subcontractor. As required by Executive Order, our US employees are required to be fully vaccinated against COVID-19 regardless of the employee’s work location or work arrangement (e.g., telework, remote work, etc.), subject to such exceptions as required by law. If selected, you will be required to be vaccinated against COVID-19 and submit documentation of proof of vaccination by December 8, 2021. AMD will provide additional information regarding what information or documentation will be needed and how you can request an exception from this requirement if you have a need for a religious and/or medical accommodation. 
#LI-DC1