Title: ASIC Power lead

The Role: ASIC Power lead responsible for PCIe IP design and power optimization 

The Person : 

• Exhibits relentless commitment to help the team meet quality and development goals on schedule
• Drives to learn and perform at his or her highest potential in a technical capacity
• Thrives in both a team environment and in individual contribution
• Communicates openly and clearly in meetings, presentations, emails, and reports
• Able to learn independently and acquire new skills required for the job
• Flexible in working hours to accommodate working with co-workers in different time-zones
• Creative and innovator and thinker who loves technical problems and detail-oriented tasks

Responsibilities :

• PCIe overall power architecture and roadmap
• Drive new power feature adoption and identifying RTL power bugs 
• Apply low power design techniques to existing logic and maintain overall system performance. 
• IP RTL design for AMDs PCI Express (PCIe) IP used for all next-generation servers, clients, GPU, and Semi-custom products.
• Work closely with IP and system architects to micro-architect cutting edge features.
• Focus on timing, LINT, and CDC closure to ensure high-quality RTL. 
• Support verification and debug of the ASIC throughout various stages of the project. 
• Jump into the lab and solve post-silicon bring-up or customer issues.

Required Skilled Sets :

• Digital Design in RTL, Verilog HDL
• Depth knowledge and experience with :
  • Voltage and Power Domain methodology
  • Clock Gating, and Clock Gating Efficiency Metrics
  • Power Gating & State Retention
  • Dynamic Clocking & Voltage Scaling
  • Specify Power Intent through UPF
• A good understanding of PCI Express and Computer Architecture is preferred. 
• During bring up, some lab work with a logic analyzer and oscilloscope might be required.
• Understanding of Linting / CDC tools, equivalence checks

Education Requirements

• Bachelor/Master in Electrical/Computer Engineering/Engineering Science or Computer Science